This invention relates generally to the field of using test probes for integrated circuit testing of devices under test [DUT].
Nondestructive methods for testing integrated circuits are known to people skilled in the art of semiconductor fabrication. Integrated circuits are generally formed or grown layer by layer on chips identified on thin planar substrates called wafers. Before the wafer is cut into individual chips, the chip circuitry must be inspected and checked.
Test procedures are usually performed while the circuits still reside together on a single wafer, since testing after the dies have been sawn apart and packaged is prohibitively expensive. Hundreds of separate devices on every wafer are analyzed by passing input signals into each device and monitoring voltage levels at selected output locations on the tiny circuits.
Previous test methods use a moving needle-like probe that moves down and scans across the two planar dimensions of the substrate. Irrespective of whether the tester is guided to a particular input-output pad on the chip or the wafer is maneuvered under an axially guided probe, a limitation in the existing technology is that difficulty is encountered in controlling the compression force that is developed when the test probe touches its target DUT.
The circuit that is tested typically comprises many strata of conductive, insulative, and semiconductive materials. The force delivered by the probe must be kept within narrow predetermined limits. If the probe pushes too hard, the device under test can be severely damaged or the excessive wear caused by the immoderate compression and friction will contribute to the premature failure of the test probe.
The pressure of the contact must, however, exceed a threshold level so that an electrical connection is made to a conductive layer through the non-conducting lamina of oxide and contaminants that coat the top of the wafer.
Another limitation of currently available test systems is a tendency for faulty registration of the test probe on its target on the wafer. Probes that are disposed to wander or slide away from the desired target area on the chip after they make contact can seriously impair the authenticity of test results or damage the surrounding circuitry.
Each of these obstacles currently confronts engineers and technicians using conventional test equipment and each will prove more deleterious as integrated circuits become more complex. As the discrete components which they comprise shrink in size, it will become more difficult to precisely manipulate a fine, pin-like probe to place the probe at a microscopic destination on the face of a computer chip DUT.
The dual problems of (a) providing precise contact forces on the die DUT, and (b) constraining motion of the probe to translation along an axis that is perpendicular to the planar surface of the die DUT, each present a challenge to designers in the semiconductor business.
The development of an improved test probe which could overcome these critical impediments would represent a major technological advance in the field of integrated circuit fabrication. The enhanced levels of quality control and test reliability that could be achieved using such an innovative device would satisfy a long felt need within the industry and would enable chip manufacturers to save substantial expenditures of time and money.
The invention described here, and defined by the claims, offers a test probe for providing precisely controlled contact forces on an integrated circuit during a test procedure. Although the invention is primarily intended for use as part of an automated test system, this novel force delivery method and apparatus may be employed in any situation which requires a carefully guided placement of one or more electrical conductors on another.